1) Field of the Invention
The present invention relates generally to the fabrication of capacitors and particularly to a method for fabricating a highly integrated semiconductor memory having a capacitor with multiple pillars and more particularly to a method for forming a capacitor having a multiple pillar structure.
2) Description of the Prior Art
The development of the semiconductor industry has always followed that of the Dynamic Random Access Memory (DRAM) technology in that DRAM development has led in the use of the highest density technology elements capable of being produced in manufacturable quantities. Problems, such as alpha-particle soft errors and maintaining minimum signal-to-noise ratios, require capacitors for DRAMs to have a maximum capacitance per memory cell area. However, the memory cell area is reduced by at least 200% for each new generation. With this trend in memory cell miniaturization, maintaining a nearly unscaled capacitance value is a challenge that requires substantial engineering effort and inventive ingenuity. The development of DRAM's in the 4 Megabit density range began to depart from the twenty year tradition of two-dimensional DRAM designs by the appearance of three-dimensional DRAM cell structures, most notable by the use of trench capacitors. Proposed designs for DRAM cells in 16 MB, 64 MB and high density range have also included the use of multi-plate or stacked storage capacitor cell designs. Although the use of stacked cell technology has rendered the processing of DRAMs more complex such techniques continue to be used extensively.
The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box, structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suitable for an integrated memory cell which is 64 Mb or higher. Also, an improved stacked capacitor has recently been presented, where pillars or another inner cylinder is formed in the interior of another cylinder. Not only may both of the inner and outer surfaces of the cylinder be utilized as the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder. However, even more surface area and capacitance are required to achieve higher densities. This invention relates to a process for increasing the capacitance of a multi-pillar capacitor.
The following U.S. patents show related processes and capacitor structures. U.S. Pat. No. 5,336,630 (Yun) shows a method of forming pillars using a glass mask having phase shifters, secondarily photo exposing the substrate under the condition of rotating 90.degree. the substrate to form a check-board photo resist pattern and patterning the polysilicon film using the photoresist pattern as a mask. U.S. Pat. No. 5,459,095 (Huang) shows a method of forming pillars using a photoresist mask to etch holes in an oxide over a polysilicon layer. U.S. Pat. No. 5,302,540 (Ko et al.) teaches a method of forming pillars using a hemispherical polysilicon layer over an oxidation barrier layer over a bottom polysilicon layer. The hemispherical polysilicon layer is oxidized and used as an etch mask to etch pillars in the bottom polysilicon layer. U.S. Pat. No. 5,427,974 (Lur et al.) teaches a method where a RIE etchback of a rough tungsten layer forms islands of TiN in the underlying TiN layer. The TiN islands are used as an etch mask to form pillars in an underlying polysilicon layer. U.S. Pat. No. 5,459,095 (Huang) teaches a method of forming pillars using a photoresist mask to etch holes in an oxide over a polysilicon layer.
However, many of these methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. Therefore, it is very desirable to develop processes that are as simple as possible and also have large process windows.
There is also a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. There is also a challenge to develop a method to produce a capacitor with a minimum leakage current, a larger capacitance, a higher reliability and which is easy to manufacture.